Memory partitioning for Dynamatic
Description #
Practical work on Dynamatic, an open-source high-level synthesis compiler that turns C into dynamically scheduled hardware circuits — unlike classical HLS, the schedule is decided at runtime by handshaking between components, so the circuit can exploit parallelism that a static schedule has to give up on.
That advantage disappears at the memory interface. Every access funnelled through a single memory port serialises, and the dataflow circuit stalls waiting on it. The work was to implement memory partitioning in the compiler: analysing array access patterns in the LLVM/MLIR representation, splitting arrays across multiple banks so independent accesses can proceed in parallel, and generating the corresponding memory interfaces in the emitted circuit.
Evaluation ran the partitioned and unpartitioned versions of standard HLS benchmark kernels through the toolchain, comparing cycle counts against the resource cost of the extra banks and arbitration logic.